An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of second conductivity type (P or N) into a semiconductor substrate of first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide a gate which provides a mask during formation of the source and drain by ion implantation. Thereafter, a drive-in step is applied to repair crystalline damage and to drive-in and activate the implanted dopant.
Several objectives influence IGFET design and fabrication. First, there is a desire to reduce the dimensions of the IGFET. Increasing the number of individual IGFETs that can be placed onto a single silicon chip or die produces increased functionality per chip. Second, there is a continual desire is to improve performance, and particularly the speed, of the IGFET transistors. This pursuit is manifested in shorter conduction channel lengths. Shorter channel lengths offer increased IGFET speed and allow for a greater number of operations to be performed in less time. IGFETs are used in great quantity in computers where the push to obtain higher operation cycle speeds demands faster IGFET performance. Lastly, there exists a constant need to maintain costly IGFET fabrication steps at a minimum.
As the feature dimensions of the IGFET device dwindle, new performance hurdles present themselves. One particular difficulty involves contact resistance between the IGFET and different metallization layers. Contact resistance is influenced by the materials, the substrate, doping and the contact dimensions. Refractory metals and their silicides offer lower contact resistance but have other limitations, such as for use in a self-alignment process. Refractory metals are popular for filling via holes, a process known as plug filling, in multi-level metal structures. Polysilicon, on the other hand, has been more popular for use as gate contact due to their utility for producing "self -aligned" source/drain regions. A gate formed from polysilicon structure will serve as a mask whereby the subsequent source/drain doping aligns the dopants next to the gate. Polysilicon is also well suited for the salicidation process where self-alignment technique is combined with an additional layer of a refractory metal silicide. The silicide is formed by reaction of the refractory metal with the underlying polysilicon through an alloy step. There have been serious efforts on the use of tungsten and other refractory metal gates as a mask in a self-aligned process. However, even though these metals tolerate high temperatures, their thermal budget tends to limit anneal temperatures for the source/drain implants.
A continual need exists for creating improved junctions between the IGFET structures and subsequent metallization layers. Thus, it is desirable to produce source and drain junctions which are scalable in size and material in order to improve contact resistance. It is also desirable to form gates which offer decreased contact resistivity. Further, a method is desirable to achieve the above mentioned results while keeping costly fabrication steps to a minimum.